Taking a typical flyback power converter for example, referring to FIG. 1, a rectifier circuit 10 is used to rectify an alternating-current (AC) input voltage VAC, a capacitor Cbulk is connected to the output of the rectifier circuit 10 to stabilize the direct-current (DC) input voltage Vbulk produced by the rectifier circuit 10 to apply to the primary coil Lp of a transformer 12, a controller 14 provides a control signal GATE to switch a power switch M1 connected in series with the primary coil Lp to convert the voltage Vbulk into a DC output voltage Vo, a current sense resistor Rcs is connected in series with the power switch M1 to produce a current sense signal Vcs related to the current Ip of the power switch M1, the controller 14 has a pin COMP receiving a feedback signal derived from the DC output voltage Vo for performing negative feedback control, and the controller 14 determines the control signal GATE according to the current sense signal Vcs and a preset current limit signal. Recently, for making products more competitive, lowering costs has become one of the requirements for product development, and therefore selection of components is increasingly strict while the capacitor Cbulk is increasingly downsized. However, for systems of a same rating, when having low input voltage, the system using a smaller capacitor Cbulk will have shorter hold up time for the voltage Vbulk, so the voltage Vbulk at the primary side of the transformer 12 varies significantly, which may cause serious sub-harmonic problem when the system escapes from soft-start or becomes overloaded. Such serious sub-harmonic problem may cause the system, when fully loaded, unable to start-up with a low input voltage or lead to a significant difference between a high input voltage over current protection and a low input voltage over current protection.
FIG. 2 illustrates the addressed sub-harmonic problem in the conventional flyback power converter, in which waveform 20 represents an internal clock CLK of the controller 14, waveform 22 represents a leading-edge blanking signal LEB, waveform 24 represents the control signal GATE, waveform 26 represents the current limit signal, and waveform 28 represents the current sense signal Vcs. The clock CLK serves to determine the cycle of the control signal GATE, the leading-edge blanking signal LEB is used to blank spikes of the current sense signal Vcs when the power switch M1 turns on, and the control signal GATE turns to low to turn off the power switch M1 once the current sense signal Vcs becomes higher than the current limit signal. Under a low input voltage, the power switch M1 has a longer on time, such as from time t1 to time t2, to obtain adequate energy, and thus has a shorter off time since the power switch M1 has a constant cycle, thereby causing incomplete release of energy. As a result, when the power switch M1 turns on again, as shown at time t3, the initial level of the current sense signal Vcs will be higher than the previous one, so the current sense signal Vcs will sooner become higher than the current limit signal, as shown at time t4, and the on time of the power switch M1 is shortened accordingly. The acute variation of the on time of the power switch M1 may cause serious sub-harmonic problem to the flyback power converter.